The present invention relates to an amplifier circuit and a method for controlling the same. More particularly, the present invention relates to a self-biased amplifier circuit and a method for self-biasing an amplifier circuit.
FIG. 1 schematically illustrates a conventional voltage follower circuit driving a combination of resistive and capacitive loads. As shown in FIG. 1, an input signal (Vin) is applied to a non-inverting terminal, and an inverting terminal is coupled to an output terminal. There are a number of applications requiring a voltage follower circuit having low output impedance and capable of driving capacitive load. In many cases the load also includes a resistor in parallel with a large capacitor, for example, a resistive ladder in an analog-to-digital converter.
FIG. 2A schematically illustrates an example of a conventional operational amplifier 10 which drives a resistive load RL and a capacitive load CL. FIG. 2A also depicts an example of how the amplifier 10 could be implemented using the CMOS process (NMOS and PMOS transistors). A typical technique to drive such loads is to use a single-stage operational amplifier which is compensated at its output (Vo). As shown in FIG. 2A, the amplifier 10 includes input devices (M1 and M2), and a current mirror circuit 12 which includes two PMOS devices M3 and M4 with the device ratio of 1:k. The current mirror circuit 12 provides a load current IL at the output terminal, which is ideally the same as a current i1(when k=1) flowing through the input device M1. In general, the load current IL is expressed as IL=k(i1+xcex941), where xcex941 is an offset including a random offset of the devices due to process (and other uncontrollable factors) and a systematic offset.
However, the presence of an equivalent low resistor (RL) at the output terminal lowers the open-loop DC gain of the amplifier 10. The low open-loop DC gain results in poor DC accuracy, which in turn leads to a systematic offset between the input Vin and the output Vo. For example, if the tail current (Itail), which is the sum of the currents flowing through the input devices M1 and M2, is a constant bias current, then the varying load current (IL) with a varying input voltage Vin(or a varying load resistance RL) results in a varying systematic offset between the input and output. A zero systematic offset only occurs when             I      tail        =                            i          1                +                  i          2                    =                        2          ⁢                      I            L                          k              ,
Where k is the device ratio of the PMOS transistors M4 to M3 as mentioned above. The DC power supply rejection is also poor because of the finite drain-source conductance gds of the mirror transistors M3 and M4.
One solution to increase the DC gain is to use a two-stage (or multi-stage) amplifier. The compensation of such multi-stage circuits typically involves the use of floating capacitors (e.g. pole-splitting or nested-miller techniques). However, floating capacitors may not be available in a standard CMOS process. Another solution may be the use of an adaptive biasing technique. FIG. 2B schematically illustrates a conventional amplifier circuit 14 employing such an adaptive biasing. As shown in FIG. 2B, the tail current of the differential pair M1 and M2 is adjusted according to the load current, and this technique also improves the open-loop DC gain performance. However, the amplifier circuit 14 still has a substantial offset because the gain is similar to that of a single-stage amplifier.
An amplifier circuit includes a first input device coupled to a first input node and controlling a first current, a second input device coupled to a second input node and controlling a second current, a current source device coupled to a bias node and controlling a summed current of the first and second currents, a current mirror circuit, a first feedback circuit, a second feedback circuit, and a capacitor. The current mirror circuit generates a load current by mirroring the first current so as to provide an output signal voltage to an output node couple to the second output node. The first feedback circuit supplies a mirrored first current to the bias node, and the second feedback circuit pulls a mirrored second current from the bias node. The capacitor is coupled to the bias node and provides the bias voltage to the current source device.